1. Field of the Invention
The invention is directed generally to multiple frequency synthesis for wire-line transceivers and similar devices and, more particularly, to multiple frequency synthesis for wire-line transceivers and similar devices using fewer clock sources than the number of frequencies needed.
2. Related Art
Many devices, such as wire line transceivers, may be required to operate in conjunction with multiple operating frequencies or have a requirement for a source of multiple operating frequencies.
Some of these frequencies may be derived by applying coding schemes to the data. However, some of these frequencies may not be able to be synthesized using such techniques. The result is that in order to synthesize a number of frequencies, a similar number of clock sources, such as phase lock loop devices, must be employed in a system. This can result in increases in complexity, cost, and/or chip/circuit size.
More specifically, many network standards, such as Ethernet standards, require at least two different types of encoding of serial data. There are numerous reasons for encoding serial data. For example, data may be encoded to transform an original sequence of data into another stream that is DC balanced. Additionally, encoding the data that is transmitted in a network may facilitate having a minimum number of transitions in each data block. Moreover, encoding may be beneficial in that it allows for implementation of systems having an AC-coupled configuration. Furthermore, this may ease the tasks of clock and data recovery by providing sufficient transitions to facilitate phase blocking.
For example, one such exemplary encoding scheme is a 64 bit–66 bit (64 B/66 B) encoding scheme. The 64 B/66 B encoding scheme includes two redundancy bits that are added to a sequence of data that is 64 bits in length. When the 64 B/66 B encoding scheme is applied to a 10 Gb/s data signal, the result is an effective output rate of 10.3125 Gb/s. Another scheme for encoding data is 8 bit–10 bit (8 B/10 B) encoding scheme in which two bits are added in a sequence of 8 bits. Applying 8 B/10 B encoding scheme to a sequence of data that is operating at 2.5 Gb/s results in an effective output rate of 3.125 Gb/s. However, the requirement for multiple frequencies in turn has resulted in a requirement for multiple clock sources that results in increased complexity, cost and chip/circuit size.
Accordingly, there is a need for a device or source of multiple frequencies in communication devices such as wireline transceivers that provides a cost savings, chip size reduction and/or reduction in complexity.